Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology is well known and widely used in the electronics industry. Performance enhancement between generations of devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device “scaling.” As MOSFETs are scaled to channel lengths below 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate of the same to control whether the device is on or off. This phenomenon is called the “short-channel effect”.
Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (usually, but not limited to, silicon dioxide) below the device active region, unlike conventional “bulk” MOSFETs, which are formed directly on silicon substrates, and hence have silicon below the active region. SOI is advantageous since it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. This result is often achieved by ensuring that all the silicon in the MOSFET channel region can be either inverted or depleted by the gate (called a fully depleted SOI MOSFET). As device size is scaled, however, this becomes increasingly difficult because the distance between the source and drain is reduced. The reduced distance increases interaction with the channel, reducing gate control and increasing short channel effects.
The double-gate MOSFET structure places a second gate in the device, such that there is a gate on either side of the channel. This allows gate control of the channel from both sides, reducing short channel effects. Additionally, when the device is turned on using both gates, two conduction (“inversion”) layers are formed, allowing for more current flow or higher drive current. An extension of the double-gate concept is the “surround-gate” or “wraparound-gate” concept, where the gate is placed such that it completely or almost-completely surrounds the channel, providing better gate control.
These double-gate MOSFETs are sometimes referred to as “FinFET” structures because of their shape. One method of forming FinFET structures is by first forming channels and then source and drain regions are formed by a silicon deposition process. This results in source and drain which are necessarily taller than the channel fin, and the gate length is defined by using an oxide spatial process to create a gap between the tall source and drain islands. This gap is then filled with gate material so that the gate straddles the fin and forms a double gate device.
In a bulk type device, such as a MOSFET, the use of Si—Ge materials can increase charge carrier mobility, especially hole type carriers. A channel region containing germanium can have charge carrier mobility 2-5 times greater than a conventional Si channel region due to reduce charge carrier scattering and due to the reduced mass of holes in the germanium-containing material. According to conventional Si—Ge formation techniques for bulk-type devices, a dopant implanted molecular beam epitaxy (MBE) technique forms a Si—Ge epitaxial layer. However, the MBE technique requires very complicated, very expensive equipment and is not feasible for mass production of integrated circuits.
In silicon MOSFET devices, it has been shown that performance can be enhanced by enhancing the mobility of electrons and holes in, for example, the channel region. One way to enhance mobility is by the use of strained materials, such as strained silicon. A material under compressive stress enhances hole carrier mobility because the holes are confined to a strained area by the potential energy offset between the surrounding silicon regions and the strained area.
A silicon germanium layer can be provided in the channel region to achieve a channel region containing germanium. As transistor dimensions are minimized, the thickness of the silicon germanium layer must be very thin (e.g., less than several hundred angstroms). Conventional fabrication methods have not been able to feasibly produce strained silicon channel regions above silicon germanium layers.
Thus, there is a need for a method of growing strained silicon as a channel region to reduce source/drain junction capacitance. Further, there is a need for enhanced channel mobility. Further still, there is a need for a method of fabricating a strained silicon channel layer over a silicon germanium layer.